This invention generally relates to methods for forming shallow trench isolation (STI) features and more particularly to a method for forming an STI feature to avoid acidic etching of trench sidewalls.
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and shallow trench isolation features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily, or permanently, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is the preferred electrical isolation technique especially for a semiconductor chip with high integration. In general, conventional methods of producing an STI feature include forming a hard mask over the trench layer, patterning a photoresist etching mask over the hard mask, etching the hard mask through the photoresist etching mask to form a patterned hard mask, and thereafter etching the trench in, for example, a silicon substrate to form the STI feature. Subsequently, the photoresist etching mask is removed and the STI feature is back-filled with a dielectric material.
For example, in a typical STI formation process, STI features are etched in a sequential process flow in a multi-chamber apparatus where the mask layers are etched in one chamber and the silicon trench is etched in another chamber. Dry etching is performed by way of a plasma or reactive ion etch (RIE). Typically, in a plasma etching process an etchant source gas supplied to an etching chamber where the plasma is ignited to generate ions from the etchant source gas. Ions are then accelerated towards the process wafer surface, frequently by a voltage bias, where they impact and remove material (etch) from the process wafer. Various gas chemistries are used to provide variable etching rates for different etching target materials. Frequently used dry etchant source gases include fluoro-hydrocarbons to etch through a metal nitride layer for example silicon nitride (SiN), and chlorine (Cl2) and HBr to etch through a silicon layer to form the etched shallow trench isolation (STI) feature.
In forming the STI structures, one technique involves the layering of dielectric films on a silicon substrate. A typical prior art process begins with a silicon substrate, upon which a thin layer of silicon dioxide is formed, for example about 100 Angstroms, referred to a pad oxide, to minimize thermal stresses in subsequent processing steps. Following the pad oxide deposition, a substantially thicker layer of silicon nitride is deposited over the silicon nitride layer, for example, about 1800 Angstroms. The silicon nitride layer is photolithographically patterned and etched to form a hard mask pattern for subsequent etching of a trench feature for an STI structure. After stripping of the photoresist by an oxygen containing dry plasma etching process, trenches are etched into an underlying silicon layer. In a typical process, the trench may be then lined with a dielectric layer such as silicon oxynitride and then filled with an insulating oxide, for example silicon dioxide, by an HDP-CVD process. A CMP planarization process is then used to remove excess oxide with the silicon nitride layer acting as a polishing stop. Subsequently, the silicon nitride layer is removed by a wet etching process with hot phosphoric acid.
Recently, in the manufacture of ultra low power and other semiconductor devices, it has become advantageous to isotropically etchback the silicon nitride layer following the trench etching process to etchback the sidewalls of the silicon nitride layer overlying the trench. After etchback the width of the trench opening is smaller than the width of the silicon nitride hardmask opening overlying the trench to leave an exposed recessed area surrounding the trench. The etchback process leaving an exposed recessed area surrounding the trench has been found advantageous to improve device performance where critical dimensions in the active device area involve forming smaller linewidths, for example, in 0.15 micron and 0.13 micron technology devices. For example, referring to FIG. 1A is shown a silicon nitride layer 16 overlying a semiconductor substrate 12 having a patterned photoresist layer 18 overlying the silicon nitride layer 16 following anisotropic etching of the silicon nitride layer 16 to form a hardmask opening 20A according to the patterned photoresist layer 18. In FIG. 1B is shown an STI trench 20B following a second anisotropic etching step according to the hardmask opening 20A. Following the trench etching step, the photoresist layer 18 is removed by an ashing process. According to the prior art process, a wet etching process is carried out to isotropically etchback the silicon nitride layer 16 to increase the width of the hardmask opening 20A relative to the width of the trench opening 20B as shown in FIG. 1C thereby forming an exposed recessed area 20C. According to prior art processes, the silicon nitride layer 16 is isotropically etched back using phosphoric acid H3PO4 where the semiconductor wafer is dipped for a period of time to isotropically etch back the silicon nitride layer.
One problem according to the prior art is that the wet etchback process typically causes acidic etching damage to the STI feature surfaces including roughening of the sidewall surfaces of the trench. Acidic etching (roughening) of the STI surfaces including the sidewall surfaces can cause electrical isolation reliability concerns, for example reducing adhesion between a subsequently deposited silicon oxy-nitride trench liner, and enhancing undesirable doping segregation from subsequent ion implantation processes at the trench sidewalls. In some cases, the trench defects and may be severe enough to reduce a semiconductor wafer processing yield. Another problem with the prior art is that the necessity for carrying out the ex-situ wet etching process leads to increased processing times and therefore increased costs since it is necessary to remove the process wafer from the multi-chamber etching apparatus to perform the wet etchback process. Yet another shortcoming is the increased costs for safely handling and disposing of the phosphoric acid containing wet etching solution.
These and other deficiencies and shortcomings demonstrate a need in the semiconductor processing art to develop a method for increasing a width of a hardmask opening surrounding a shallow trench isolation feature following trench etching while avoiding acidic etching of shallow trench isolation features.
It is therefore an object of the invention to provide a method for increasing a width of a hardmask opening surrounding a shallow trench isolation feature following trench etching while avoiding acidic etching of shallow trench isolation features while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a shallow trench isolation feature to avoid acidic etching of trench sidewalls.
In a first embodiment according to the present invention, the method includes the steps of providing a semiconductor substrate having an overlying silicon nitride layer; photolithographically patterning the silicon nitride layer to expose a portion of the silicon nitride layer; anisotropically etching through a thickness of the portion of the silicon nitride layer to form a hardmask opening exposing a portion of the semiconductor substrate; blanket depositing a polymer layer according to a plasma deposition process including at least partially covering the sidewalls and bottom portion of the hardmask opening; and, anisotropically etching a trench opening through a thickness portion of the semiconductor substrate according to the hardmask opening.
In related embodiments, the semiconductor substrate comprises at least one of single crystalline silicon and polycrystalline silicon. Further, the step of blanket depositing a polymer layer includes at least partially filling the hardmask opening.
In another embodiment, the plasma deposition process includes supplying at least one fluoro-hydrocarbon to form a plasma for depositing the polymer layer. Further, the at least one fluoro-hydrocarbon includes fluoro-hydrocarbons with a fluorine to carbon ratio of less than about 4. Further yet, the fluoro-hydrocarbon includes CH2F2.
In another embodiment, the trench opening is anisotropically etched to have a trench opening width less than a width of the hardmask opening. Further, the trench opening width is less than the width of the hardmask opening by about 10 to about 100 nanometers.
In yet another embodiment, the trench opening is anisotropically etched such that trench corners including a top and bottom portion of the trench opening are partially rounded having a radius of curvature.
In yet a further embodiment, the method includes the step of carrying out a plasma etching ashing process following the step of anisotropically etching a trench opening to remove polymer materials including the polymer layer. Further, the steps including and following anisotropically etching through a thickness of the portion of the silicon nitride layer are carried out in a single processing chamber to comprise in-situ process steps.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.